module down_link_ctrl(
		//input
		clk_1m,
		rst_n,
		jud_err,
		end_flag,
		time_out,
		up_link_req,
		sram_ack,
        test_mode,
        time_20ms,
		//
		oe_8ch,
		down_link_req,
		down_sram_wr,
		down_sram_addr,
		down_sram_data,
		wr_sram_req,
		init_resp_req,
		sram_mux,
        ch_125k_en,
        oe_timer
);
parameter  N = 8;
input clk_1m;
input rst_n;
input [N-1:0] jud_err;
input [N-1:0] end_flag;
input time_out;
input up_link_req;
input sram_ack;
input test_mode;
input time_20ms;

output [7:0] oe_8ch;
output down_link_req;
output down_sram_wr;
output [12:0] down_sram_addr;
output [N-1:0]down_sram_data;
output wr_sram_req;
output init_resp_req;
output sram_mux;
output [1:0] ch_125k_en;
output oe_timer;

wire wr_sram_done;
wire [7:0]	Result0,Result1,Result2,Result3,
			Result4,Result5,Result6,Result7;
wire wr_sram_req;
wire init_resp_req;
wire init_resp_done;
wire down_sram_wr;
wire [12:0] down_sram_addr;
wire [7:0]  down_sram_data;

	 
	 
	 
  control control_ins( 
	//input
	.clk_1m(clk_1m),
	.rst_n(rst_n),
	.jud_err(jud_err),
	.end_flag(end_flag),
	.time_out(time_out),
	.up_link_req(up_link_req),
	.wr_sram_done(wr_sram_done),
	.init_resp_done(init_resp_done),
    .test_mode(test_mode),
    .time_20ms(time_20ms),
	//output
	.oe_8ch(oe_8ch),
	.down_link_req(down_link_req),
	.Result0(Result0),
	.Result1(Result1),
	.Result2(Result2),
	.Result3(Result3),
	.Result4(Result4),
	.Result5(Result5),
	.Result6(Result6),
	.Result7(Result7),
	.wr_sram_req(wr_sram_req),
	.init_resp_req(init_resp_req),
	.sram_mux(sram_mux),
    .ch_125k_en(ch_125k_en),
    .oe_timer(oe_timer)
);

write_sram  wr_sram_ins(
			//input
			.clk_1m(clk_1m),
			.rst_n(rst_n),
			.wr_sram_req(wr_sram_req),
			.init_resp_req(init_resp_req),
			.sram_ack(sram_ack),
			
			.status0(Result0),
			.status1(Result1),
			.status2(Result2),
			.status3(Result3),
			.status4(Result4),
			.status5(Result5),
			.status6(Result6),
			.status7(Result7),
			//output
			.sram_wr(down_sram_wr),
			.sram_addr(down_sram_addr),
			.sram_data(down_sram_data),
			.wr_sram_done(wr_sram_done),
			.init_resp_done(init_resp_done)
	);
		

endmodule 